The present invention relates to a semiconductor manufacturing process and in particular to a method of forming an epitaxy layer of uniform and flat surface.
Currently, deep-submicron complementary metal oxide semiconductor (CMOS) is the primary technology for ultra-large scale integrated (ULSI) devices. Over the last two decades, reducing the size of CMOS transistors and increasing the number of transistors on chip have held principal focus in the microelectronics industry. An ultra-large scale integrated circuit can include over 1 million transistors.
The ULSI circuit can include CMOS field effect transistors (FETS) with semiconductor gates disposed between drain and source regions. The drain and source regions are typically heavily doped with a P-type dopant (boron) or an N-type dopant (phosphorous). The drain and source regions generally include a thin extension disposed partially underneath the gate to enhance the transistor performance. Shallow source and drain extensions help to achieve immunity to short-channel effects that degrade transistor performance for both N-channel and P-channel transistors. Short-channel effects can cause threshold voltage roll-off and drain-induced barrier-lowering. Shallow source and drain extensions and, therefore controlling short-channel effects, are particularly important as transistors become smaller.
As the size of transistors disposed on ICs decreases, transistors with shallow and ultra-shallow source/drain extensions become more difficult to manufacture. For example, a small transistor may require ultra-shallow source and drain extensions with less than 30 nanometer (nm) junction depth. The source and drain junction depths also scale with the junction depth of source and drain extensions. During subsequent silicidation process on the source and drain extensions, silicide may penetrate the source and drain junctions, resulting in junction leakage issue. Raised source and drain, therefore, is now introduced to improve junction leakage by forming additional Si on the source/drain regions in the substrate for silicidation consumption. Similarly, raised source and drain is also utilized for silicon-on-insulator (SOI) application. Typical silicon thickness on the oxide layer is 100˜200 Å for fully depleted SOI structure. Silicidation process may consume all of the silicon above the oxide layer if without raised source and drain.
The raised source and drain regions are conventional formed by dpositing epitaxial silicon on the source and drain regions in the substrate. The raised source and drain regions provide additional material for contact silicidation processes and reduce junction leakage. In the conventional art, shallow source and drain extensions are first formed in a substrate. Pure silicon (Si) selective epitaxy growth (SEG) is then performed to form an elevated source and an elevated drain, i.e. raised source and drain.
Furthermore, conventional technology also uses Silicon Germanium (SiGe) selective epitaxy growth (SEG) to form raised source/drain regions. This process can be performed at lower temperature than that used in pure Si selective epitaxy growth for thermal budget reduction considerations. However, silicon germanium (SiGe) selective epitaxy growth (SEG), makes silicidation of the raised extensions difficult. Yu, in U.S. Pat. Nos. 6,218,711 and 6,479,358, the entirety of each of which are hereby incorporated by reference, describes a raised source/drain process by epitaxy, using a method of forming a raised source/drain comprising germanium of gradient concentration to overcome difficulty of silicidation.
Furthermore, epitaxial layers are also utilized for other applications. For example, Yeo et al., in U.S. Pat. No. 6,492,216, the entirety of which is hereby incorporated by reference, describes a method of forming a tensile or compressive strained channel region for a semiconductor device, such as a MOSFET device, allowing improved carrier transport properties and increased device performance to be realized. The strained channel layer composed of silicon-germanium-carbon layer is formed utilizing ultra high vacuum chemical vapor deposition (UHVCVD).